Scalable, Secure Chip Design is Focus of New DARPA Effort

Automatic Implementation of Secure Silicon (AISS)

Building security into modern semiconductor chips is more than a technical challenge — it is a complex mix of economic and technology tradeoffs.  Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. 

A new research effort by the Defense Advanced Research Agency (DARPA) — the Automatic Implementation of Secure Silicon (AISS) program — seeks to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity.

AISS is part of the second phase of DARPA’s Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. Under ERI Phase II, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections. AISS will help address this mission through its efforts to enable scalable on-chip security.

A Broad Area Announcement (BAA) is forthcoming.  DARPA will hold a Proposers Day on April 10, 2019 at the DARPA Conference Center, located at 675 North Randolph Street, Arlington, Virginia 22203, to provide more information about AISS and answer questions from potential proposers.

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